Datasheet

Section 8 I/O Ports
Rev. 2.00 Aug. 20, 2008 Page 212 of 1198
REJ09B0403-0200
Latch
Pin input
Sampling clock selection
Sampling clock
Match
detection
circuit
Port data
register
Latch
Latch
φ/2, φ/32, φ/512, φ/8192,
φ/32768, φ/65536,
φ/131072, φ/262144
∆t
Figure 8.3 Noise Canceler Circuit
P4n input
1 expected
P4nDR
0 expected
P4nDR
(n = 7 to 4)
Figure 8.4 Noise Canceler Operation