Datasheet

Section 8 I/O Ports
Rev. 2.00 Aug. 20, 2008 Page 216 of 1198
REJ09B0403-0200
8.1.5 Port 5
Port 5 is an 8-bit I/O port. Port 5 pins can also function as the SCIF, SCI_1, and SSU input/output,
bus control output, system clock output, external subclock input, and interrupt input pins. Port 5
has the following registers.
• Port 5 data direction register (P5DDR)
• Port 5 data register (P5DR)
(1) Port 5 Data Direction Register (P5DDR)
The individual bits of P5DDR specify input or output for the port 5 pins.
Bit Bit Name Initial Value R/W Description
7 P57DDR 0 W If port 5 pins are specified for use as the general I/O
port, the corresponding pins function as output port
when the P5DDR bits are set to 1, and as input port
when cleared to 0.
6 P56DDR 0 W The corresponding port 5 pin functions as the system
clock output pin (φ) when this bit is set to 1, and as
the general I/O port when cleared to 0.
5 P55DDR 0 W
4 P54DDR 0 W
3 P53DDR 0 W
2 P52DDR 0 W
1 P51DDR 0 W
0 P50DDR 0 W
If port 5 pins are specified for use as the general I/O
port, the corresponding pins function as output port
when the P5DDR bits are set to 1, and as input port
when cleared to 0.