Datasheet

Rev. 2.00 Aug. 20, 2008 Page xxvi of xlviii
26.2 Input/Output Pins............................................................................................................. 1019
26.3 Register Descriptions....................................................................................................... 1020
26.3.1 Instruction Register (SDIR)................................................................................ 1021
26.3.2 Bypass Register (SDBPR) .................................................................................. 1022
26.3.3 Boundary Scan Register (SDBSR) ..................................................................... 1022
26.3.4 ID Code Register (SDIDR)................................................................................. 1040
26.4 Operation ......................................................................................................................... 1041
26.4.1 TAP Controller State Transitions........................................................................ 1041
26.4.2 JTAG Reset......................................................................................................... 1042
26.5 Boundary Scan................................................................................................................. 1042
26.5.1 Supported Instructions ........................................................................................ 1042
26.6 Usage Notes ..................................................................................................................... 1045
Section 27 Clock Pulse Generator...................................................................1049
27.1 Oscillator.......................................................................................................................... 1050
27.1.1 Connecting Crystal Resonator ............................................................................ 1050
27.1.2 External Clock Input Method.............................................................................. 1051
27.2 PLL Multiplier Circuit ..................................................................................................... 1052
27.3 Medium-Speed Clock Divider ......................................................................................... 1052
27.4 Bus Master Clock Select Circuit...................................................................................... 1052
27.5 Subclock Input Circuit..................................................................................................... 1052
27.6 Subclock Waveform Shaping Circuit .............................................................................. 1052
27.7 Clock Select Circuit ......................................................................................................... 1053
27.8 Usage Notes ..................................................................................................................... 1054
27.8.1 Note on Resonator .............................................................................................. 1054
27.8.2 Notes on Board Design....................................................................................... 1054
27.8.3 Note on Operation Check ................................................................................... 1054
Section 28 Power-Down Modes...................................................................... 1055
28.1 Register Descriptions....................................................................................................... 1056
28.1.1 Standby Control Register (SBYCR) ................................................................... 1056
28.1.2 Low-Power Control Register (LPWRCR) .......................................................... 1059
28.1.3 Module Stop Control Registers H, L, and A
(MSTPCRH, MSTPCRL, MSTPCRA) .............................................................. 1060
28.1.4 Sub-Chip Module Stop Control Registers BH, BL
(SUBMSTPBH, SUBMSTPBL)......................................................................... 1062
28.2 Mode Transitions and LSI States..................................................................................... 1063
28.3 Medium-Speed Mode....................................................................................................... 1065
28.4 Sleep Mode ...................................................................................................................... 1066
28.5 Software Standby Mode................................................................................................... 1067