Datasheet

Section 8 I/O Ports

Rev. 2.00 Aug. 20, 2008 Page 244 of 1198

REJ09B0403-0200

• PA4/ExIRQ4/EVENT4/A20, PA3/ExIRQ3/EVENT3/A19, PA2/ExIRQ2/EVENT2/A18

The pin function is switched as shown below according to the setting of address 18 and the

PAnDDR bit.

Setting the ISSn bit in ISSR makes the pin to function as the ExIRQn input pin.

When using the pin as the ExIRQn input or an EVENT input pin, clear the PAnDDR bit to 0.

Though the settings for the EVENT input pin have been made, set the PAnDDR bit to 1 when

using the pin as the PAn or Am output pin.

PAnDDR 0 1 1

Address 18 X 1 0

PAn input pin Pin function

ExIRQn input pin/EVENTn input pin

PAn output pin Am output pin

[Legend] n = 4 to 2, m = 20 to 18

X: Don't care

• PA1/ExIRQ1/EVENT1/A17, PA0/ExIRQ0/EVENT0/A16

The pin function is switched as shown below according to the setting of address 13 and the