Datasheet

Section 8 I/O Ports
Rev. 2.00 Aug. 20, 2008 Page 250 of 1198
REJ09B0403-0200
(4) Noise Canceler Enable Register (P4BNCE)
P4BNCE enables or disables the noise canceler circuits of port 4 and port B pins in bit units.
Bit Bit Name Initial Value R/W Description
7 to 4 P47NCE to
P44NCE
All 0 R/W Bits for port 4 setting
3 PB3NCE 0 R/W
2 PB2NCE 0 R/W
1 PB1NCE 0 R/W
0 PB0NCE 0 R/W
Enables the noise canceler circuit for the corresponding
pin and the pin state is fetched into PBDR at the
sampling cycle set by NCCS.
The operation changes according to the other control
bits. See section 8.1.11 (7), Pin Functions, for details.
(5) Noise Canceler Mode Control Register (P4BNCMC)
P4BNCMC controls whether 1 or 0 is expected for the input signal to port 4 and port B in bit
units.
Bit Bit Name Initial Value R/W Description
7 to 4 P47NCMC
to
P44NCMC
All 1 R/W Bits for port 4 setting
3 PB3NCMC 1 R/W
2 PB2NCMC 1 R/W
1 PB1NCMC 1 R/W
0 PB0NCMC 1 R/W
Expected value setting
1 expected: 1 is stored in the port data register while 1
is input stably.
0 expected: 0 is stored in the port data register while 0
is input stably.