Datasheet

Rev. 2.00 Aug. 20, 2008 Page xxix of xlviii
Figures
Section 1 Overview
Figure 1.1 Internal Block Diagram................................................................................................ 3
Figure 1.2 Pin Assignments (H8S/2472 Group)............................................................................ 4
Figure 1.3 Pin Assignments (H8S/2463 Group)............................................................................ 5
Figure 1.4 Pin Assignments (H8S/2462 Group)............................................................................ 6
Section 2 CPU
Figure 2.1 Exception Vector Table (Normal Mode).................................................................... 29
Figure 2.2 Stack Structure in Normal Mode................................................................................ 29
Figure 2.3 Exception Vector Table (Advanced Mode)................................................................ 30
Figure 2.4 Stack Structure in Advanced Mode............................................................................ 31
Figure 2.5 Memory Map.............................................................................................................. 32
Figure 2.6 CPU Registers ............................................................................................................ 33
Figure 2.7 Usage of General Registers ........................................................................................ 34
Figure 2.8 Stack........................................................................................................................... 35
Figure 2.9 General Register Data Formats (1)............................................................................. 38
Figure 2.9 General Register Data Formats (2)............................................................................. 39
Figure 2.10 Memory Data Formats .............................................................................................40
Figure 2.11 Instruction Formats (Examples) ............................................................................... 52
Figure 2.12 Branch Address Specification in Memory Indirect Mode........................................ 56
Figure 2.13 State Transitions....................................................................................................... 60
Section 3 MCU Operating Modes
Figure 3.1 Address Map ..............................................................................................................69
Section 4 Exception Handling
Figure 4.1 Reset Sequence........................................................................................................... 75
Figure 4.2 Stack Status after Exception Handling ....................................................................... 77
Figure 4.3 Operation When SP Value is Odd.............................................................................. 78
Section 5 Interrupt Controller
Figure 5.1 Block Diagram of Interrupt Controller....................................................................... 80
Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0............................................................. 89
Figure 5.3 Block Diagram of Interrupt Control Operation .......................................................... 93
Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0 .....96
Figure 5.5 State Transition in Interrupt Control Mode 1 ............................................................. 97
Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1.... 99
Figure 5.7 Interrupt Exception Handling................................................................................... 100
Figure 5.8 Interrupt Control for DTC ........................................................................................ 102