Datasheet

Section 8 I/O Ports
Rev. 2.00 Aug. 20, 2008 Page 262 of 1198
REJ09B0403-0200
• PD4/CLKRUN
The pin function is switched as shown below according to the PD4DDR bit. This pin can be
used as the CLKRUN input pin when the LPC is enabled.
LPC Disabled Enabled
PD4DDR 0 1 0
Pin function PD4 input pin PD4 output pin CLKRUN input/output pin
• PD3/GA20
The pin function is switched as shown below according to the combination of the FGA20E bit
in HICR0 of the LPC and the PD3DDR bit.
FGA20E 0 1
PD3DDR 0 1 0
Pin function PD3 input pin PD3 output pin GA20 output pin
• PD2/PME
The pin function is switched as shown below according to the combination of the PMEE bit in
HICR0 of the LPC and the PD2DDR bit.
PMEE 0 1
PD2DDR 0 1 0
Pin function PD2 input pin PD2 output pin PME output pin
• PD1/LSMI
The pin function is switched as shown below according to the combination of the LSMIE bit in
HICR0 of the LPC and the PD1DDR bit.
LSMIE 0 1
PD1DDR 0 1 0
Pin function PD1 input pin PD1 output pin LSMI output pin