Datasheet

Section 8 I/O Ports
Rev. 2.00 Aug. 20, 2008 Page 266 of 1198
REJ09B0403-0200
• PE6/LCLK
The pin function is switched as shown below according to whether the LPC is enabled or
disabled and the PE6DDR bit.
LPC Disabled Enabled
PE6DDR 0 1 X
Pin function PE6 input pin PE6 output pin LCLK input pin
[Legend] X: Don't care.
• PE5/LRESET
The pin function is switched as shown below according to whether the LPC is enabled or
disabled and the PE5DDR bit.
LPC Disabled Enabled
PE5DDR 0 1 X
Pin function PE5 input pin PE5 output pin LRESET input pin
[Legend] X: Don't care.
• PE4/LFRAME
The pin function is switched as shown below according to whether the LPC is enabled or
disabled and the PE4DDR bit.
LPC Disabled Enabled
PE4DDR 0 1 X
Pin function PE4 input pin PE4 output pin LFRAME input pin
[Legend] X: Don't care.
• PE3/LAD3
The pin function is switched as shown below according to whether the LPC is enabled or
disabled and the PE3DDR bit.
LPC Disabled Enabled
PE3DDR 0 1 X
Pin function PE3 input pin PE3 output pin LAD3 input/output pin
[Legend] X: Don't care.