Datasheet

Section 8 I/O Ports
Rev. 2.00 Aug. 20, 2008 Page 267 of 1198
REJ09B0403-0200
• PE2/LAD2
The pin function is switched as shown below according to whether the LPC is enabled or
disabled and the PE2DDR bit.
LPC Disabled Enabled
PE2DDR 0 1 X
Pin function PE2 input pin PE2 output pin LAD2 input/output pin
[Legend] X: Don't care.
• PE1/LAD1
The pin function is switched as shown below according to whether the LPC is enabled or
disabled and the PE1DDR bit.
LPC Disabled Enabled
PE1DDR 0 1 X
Pin function PE1 input pin PE1 output pin LAD1 input/output pin
[Legend] X: Don't care.
• PE0/LAD0
The pin function is switched as shown below according to whether the LPC is enabled or
disabled and the PE0DDR bit.
LPC Disabled Enabled
PE0DDR 0 1 X
Pin function PE0 input pin PE0 output pin LAD0 input/output pin
[Legend] X: Don't care.