Datasheet

Rev. 2.00 Aug. 20, 2008 Page xxxi of xlviii
Figure 7.5 Memory Mapping in Normal Mode ......................................................................... 178
Figure 7.6 Memory Mapping in Repeat Mode ..........................................................................179
Figure 7.7 Memory Mapping in Block Transfer Mode ............................................................. 180
Figure 7.8 Chain Transfer Operation......................................................................................... 181
Figure 7.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode) ....................182
Figure 7.10 DTC Operation Timing (Example of Block Transfer Mode,
with Block Size of 2).............................................................................................. 183
Figure 7.11 DTC Operation Timing (Example of Chain Transfer) ........................................... 183
Section 8 I/O Ports
Figure 8.1 Noise Canceler Circuit ............................................................................................. 205
Figure 8.2 Noise Canceler Operation ........................................................................................ 206
Figure 8.3 Noise Canceler Circuit ............................................................................................. 212
Figure 8.4 Noise Canceler Operation ........................................................................................ 212
Figure 8.5 Noise Canceler Circuit ............................................................................................. 251
Figure 8.6 Noise Canceler Operation ........................................................................................ 252
Figure 8.7 Noise Canceler Circuit ............................................................................................. 288
Figure 8.8 Noise Canceler Operation ........................................................................................ 289
Figure 8.9 Noise Canceler Circuit ............................................................................................. 295
Figure 8.10 Noise Canceler Operation ......................................................................................295
Figure 8.11 Noise Canceler Circuit ...........................................................................................335
Figure 8.12 Noise Canceler Operation ......................................................................................336
Section 9 14-Bit PWM Timer (PWMX)
Figure 9.1 PWMX (D/A) Block Diagram .................................................................................359
Figure 9.2 PWMX (D/A) Operation.......................................................................................... 367
Figure 9.3 Output Waveform (OS = 0, DADR corresponds to T
L
) ........................................... 370
Figure 9.4 Output Waveform (OS = 1, DADR corresponds to T
H
)........................................... 371
Figure 9.5 D/A Data Register Configuration when CFS = 1..................................................... 371
Figure 9.6 Output Waveform when DADR = H'0207 (OS = 1) ................................................ 372
Section 10 16-Bit Free-Running Timer (FRT)
Figure 10.1 Block Diagram of 16-Bit Free-Running Timer ...................................................... 376
Figure 10.2 Increment Timing with Internal Clock Source ....................................................... 383
Figure 10.3 Timing of Output Compare A Output .................................................................... 383
Figure 10.4 Clearing of FRC by Compare-Match A Signal ......................................................384
Figure 10.5 Timing of Output Compare Flag (OCFA or OCFB) Setting.................................. 384
Figure 10.6 Timing of Overflow Flag (OVF) Setting................................................................ 385
Figure 10.7 OCRA Automatic Addition Timing ....................................................................... 386
Figure 10.8 Conflict between FRC Write and Clear.................................................................. 387
Figure 10.9 Conflict between FRC Write and Increment .......................................................... 388