Datasheet

Rev. 2.00 Aug. 20, 2008 Page xxxii of xlviii
Figure 10.10 Conflict between OCR Write and Compare-Match
(When Automatic Addition Function is Not Used)..............................................389
Figure 10.11 Conflict between OCR Write and Compare-Match
(When Automatic Addition Function is Used)..................................................... 390
Section 11 8-Bit Timer (TMR)
Figure 11.1 Block Diagram of 8-Bit Timer (TMR_0 and TMR_1)...........................................394
Figure 11.2 Block Diagram of 8-Bit Timer (TMR_Y and TMR_X).........................................395
Figure 11.3 Count Timing for Internal Clock Input...................................................................406
Figure 11.4 Timing of CMF Setting at Compare-Match ...........................................................406
Figure 11.5 Timing of Counter Clear by Compare-Match ........................................................407
Figure 11.6 Timing of OVF Flag Setting .................................................................................. 407
Figure 11.7 Conflict between TCNT Write and Counter Clear.................................................410
Figure 11.8 Conflict between TCNT Write and Increment ....................................................... 411
Figure 11.9 Conflict between TCOR Write and Compare-Match .............................................412
Section 12 Watchdog Timer (WDT)
Figure 12.1 Block Diagram of WDT......................................................................................... 416
Figure 12.2 Watchdog Timer Mode (RST/NMI = 1) Operation................................................423
Figure 12.3 Interval Timer Mode Operation..............................................................................424
Figure 12.4 OVF Flag Set Timing............................................................................................. 424
Figure 12.5 Output Timing of RESO signal .............................................................................. 425
Figure 12.6 Writing to TCNT and TCSR (WDT_0)..................................................................427
Figure 12.7 Conflict between TCNT Write and Increment ....................................................... 428
Figure 12.8 Sample Circuit for Resetting the System by the RESO Signal............................... 429
Section 13 Serial Communication Interface (SCI)
Figure 13.1 Block Diagram of SCI_1 and SCI_3...................................................................... 433
Figure 13.2 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits).................................................451
Figure 13.3 Receive Data Sampling Timing in Asynchronous Mode ....................................... 453
Figure 13.4 Relation between Output Clock and Transmit Data Phase
(Asynchronous Mode)............................................................................................ 454
Figure 13.5 Sample SCI Initialization Flowchart ...................................................................... 455
Figure 13.6 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit) ................................................... 456
Figure 13.7 Sample Serial Transmission Flowchart .................................................................. 457
Figure 13.8 Example of SCI Operation in Reception
(Example with 8-Bit Data, Parity, One Stop Bit) ...................................................458
Figure 13.9 Sample Serial Reception Flowchart (1).................................................................. 460
Figure 13.9 Sample Serial Reception Flowchart (2).................................................................. 461