Datasheet

Section 8 I/O Ports
Rev. 2.00 Aug. 20, 2008 Page 294 of 1198
REJ09B0403-0200
(5) Noise Canceler Mode Control Register (P4BNCMC)
P4BNCMC controls whether 1 or 0 is expected for the input signal to port 4 in bit units.
Bit Bit Name Initial Value R/W Description
7 P47NCMC 1 R/W
6 P46NCMC 1 R/W
5 P45NCMC 1 R/W
4 P44NCMC 1 R/W
Expected value setting
1 expected: 1 is stored in the port data register while 1
is input stably
0 expected: 0 is stored in the port data register while 0
is input stably
3 to 0 PB3NCMC
to
PB0NCMC
All 1 R/W Bits for port B setting
(6) Noise Canceler Cycle Setting Register (NCCS)
NCCS controls the sampling cycle of the noise cancelers.
Bit Bit Name Initial Value R/W Description
7 to 3  Undefined R/W Reserved
Undefined value is read from these bits.
2
1
0
NCCK2
NCCK1
NCCK0
0
0
0
R/W
R/W
R/W
These bits set the sampling cycle of the noise
cancelers.
• When φ = 34 MHz
000: 0.06 µs φ/2 100: 963.8 µs φ/32768
001: 0.94 µs φ/32 101: 1.9 ms φ/65536
010: 15.1 µs φ/512 110: 3.9 ms φ/131072
011: 240.9 µs φ/8192 111: 7.7 ms φ/262144