Datasheet

Section 8 I/O Ports
Rev. 2.00 Aug. 20, 2008 Page 297 of 1198
REJ09B0403-0200
(c) Single-Chip Mode
The relationship between register setting values and pin functions are as follows.
• P47 to P40
The pin function is switched as shown below according to the P4nDDR bit and P4nNCE bit.
When the ISSn bit in ISSR is cleared to 0 and the IRQnE bit in IER of the interrupt controller is
set to 1, the pin can be used as the IRQn input pin. To use as the IRQn input pin, clear the
P4nDDR bit to 0.
P4nDDR 0 1
P4nNCE 0 1 X
P4n input DBn input Pin function
IRQn input IRQn input
(with the noise canceler)
P4n output pin
[Legend] n = 7 to 4, X: Don't care
• P44 to P40
The pin function is switched as shown below according to the P4nDDR bit. When the ISSn bit in
ISSR is cleared to 0 and the IRQnE bit in IER of the interrupt controller is set to 1, the pin can be
used as the IRQn input pin. To use as the IRQn input pin, clear the P4nDDR bit to 0.
P4nDDR 0 1
P4n input pin Pin function
IRQn input pin
P4n output pin
[Legend] n = 3 to 0, X: Don't care