Datasheet

Rev. 2.00 Aug. 20, 2008 Page xxxvi of xlviii
Figure 18.25 IRIC Setting Timing and SCL Control (1) ...........................................................645
Figure 18.26 IRIC Setting Timing and SCL Control (2) ...........................................................646
Figure 18.27 IRIC Setting Timing and SCL Control (3) ...........................................................647
Figure 18.28 Block Diagram of Noise Canceler........................................................................ 650
Figure 18.29 Notes on Reading Master Receive Data ............................................................... 658
Figure 18.30 Flowchart for Start Condition Issuance Instruction
for Retransmission and Timing ............................................................................ 659
Figure 18.31 Stop Condition Issuance Timing .......................................................................... 660
Figure 18.32 IRIC Flag Clearing Timing When WAIT = 1 ......................................................661
Figure 18.33 ICDR Register Read and ICCR Register Access Timing in
Slave Transmit Mode ........................................................................................... 662
Figure 18.34 TRS Bit Set Timing in Slave Mode......................................................................663
Figure 18.35 Diagram of Erroneous Operation when Arbitration Lost ..................................... 665
Section 19 LPC Interface (LPC)
Figure 19.1 Block Diagram of LPC........................................................................................... 669
Figure 19.2 Typical LFRAME Timing...................................................................................... 737
Figure 19.3 Abort Mechanism ................................................................................................... 737
Figure 19.4 SMIC Write Transfer Flow ....................................................................................738
Figure 19.5 SMIC Read Transfer Flow ..................................................................................... 739
Figure 19.6 BT Write Transfer Flow......................................................................................... 740
Figure 19.7 BT Read Transfer Flow.......................................................................................... 741
Figure 19.8 GA20 Output ..........................................................................................................743
Figure 19.9 Power-Down State Termination Timing ................................................................ 748
Figure 19.10 SERIRQ Timing...................................................................................................749
Figure 19.11 Clock Start Request Timing ................................................................................. 751
Figure 19.12 HIRQ Flowchart (Example of Channel 1)............................................................755
Section 20 LPC Interface (LPC)
Figure 20.1 Configuration of EtherC......................................................................................... 760
Figure 20.2 EtherC Transmitter State Transitions ..................................................................... 779
Figure 20.3 EtherC Receiver State Transmissions ....................................................................781
Figure 20.4 RMII Frame Transmit Timing (Normal Transmission)..........................................782
Figure 20.5 RMII Frame Receive Timing (Normal Reception) ................................................ 782
Figure 20.6 RMII Frame Receive Timing (Reception with False Carrier)................................ 783
Figure 20.7 MII Management Frame Format ............................................................................ 784
Figure 20.8 1-Bit Data Write Flowchart.................................................................................... 785
Figure 20.9 Bus Release Flowchart (TA in Read in Figure 20.7)..............................................785
Figure 20.10 1-Bit Data Read Flowchart...................................................................................786
Figure 20.11 Independent Bus Release Flowchart (IDLE in Write in Figure 20.7) ..................786
Figure 20.12 Changing IPG and Transmission Efficiency ........................................................788