Datasheet

Section 8 I/O Ports
Rev. 2.00 Aug. 20, 2008 Page 337 of 1198
REJ09B0403-0200
• PB3/EVENT11/DB3/RM_RXD1, PB2/EVENT10/DB2/RM_RXD0,
PB1/EVENT9/DB1/RM_TXD1, PB0/EVENT8/DB0/RM_TXD0
The pin function is switched as shown below according to the combination of the module stop
state in the EtherC and E-DMAC and the PBnDDR bit.
EtherC,
E-DMAC
Either of them is stopped Both of them are
stopped
PBnDDR 0 1 X
Event
counter
Disabled Enabled X X
PBnNCE 0 1 X X X
Pin
function
PBn
input
DBn
input
EVENTm input PBn output pin RM_xxxx
EtherC I/O pin
[Legend] n = 3 to 0, m = 11 to 8, X: Don't care.