Datasheet

Section 9 14-Bit PWM Timer (PWMX)
Rev. 2.00 Aug. 20, 2008 Page 369 of 1198
REJ09B0403-0200
PCSR Fixed DADR Bits
PWCKX0
PWCKX1
Bit Data
C B A
CKS
Reso-
lution
T
(µs)
CFS
Base
Cycle
Conver-
sion
Cycle
TL/TH
(OS = 0/OS = 1)
Precision
(Bits)
DA3 DA2 DA1 DA0
Conversion
Cycle*
0 1 1 1 0 481.9 µs 123.36 ms 14 123.36 ms
2.1 kHz 12 0 0 30.84 ms
Always low/high output
DA13 to 0 = H'0000 to H'00FF
(Data value) × T
DA13 to 0 = H'0100 to H'3FFF
10 0 0 0 0 7.71 ms
1 1927.5 µs 123.36 ms 14 123.36 ms
0.5 kHz 12 0 0 30.84 ms
7.53
(φ/256)
Always low/high output
DA13 to 0 = H'0000 to H'003F
(Data value) × T
DA13 to 0 = H'0040 to H'3FFF
10 0 0 0 0 7.71 ms
1 0 0 1 0 1.93 ms 493.45 ms 14 493.45 ms
518.8 Hz 12 0 0 123.36 ms
Always low/high output
DA13 to 0 = H'0000 to H'00FF
(Data value) × T
DA13 to 0 = H'0100 to H'3FFF
10 0 0 0 0 30.84 ms
1 7.71 ms 493.45 ms 14 493.45 ms
129.7 Hz 12 0 0 123.36 ms
30.12
(φ/1024)
Always low/high output
DA13 to 0 = H'0000 to H'003F
(Data value) × T
DA13 to 0 = H'0040 to H'3FFF
10 0 0 0 0 30.84 ms
1 0 1 1 0 7.71 ms 1.974 s 14 1.974 s
129.7 Hz 12 0 0 0.493 s
Always low/high output
DA13 to 0 = H'0000 to H'00FF
(Data value) × T
DA13 to 0 = H'0100 to H'3FFF
10 0 0 0 0 0.123 s
1 30.84 ms 1.974 s 14 1.974 s
32.4 Hz 12 0 0 0.493 s
120.47
(φ/4096)
Always low/high output
DA13 to 0 = H'0000 to H'003F
(Data value) × T
DA13 to 0 = H'0040 to H'3FFF
10 0 0 0 0 0.123 s
1 1 0 1 0 30.84 ms 7.895 s 14 7.895 s
32.4 Hz 12 0 0 1.974 s
Always low/high output
DA13 to 0 = H'0000 to H'00FF
(Data value) × T
DA13 to 0 = H'0100 to H'3FFF
10 0 0 0 0 0.493 s
1 123.36
ms
7.895 s 14 7.895 s
8.1 Hz 12 0 0 1.974 s
481.88
(φ/16384)
Always low/high output
DA13 to 0 = H'0000 to H'003F
(Data value) × T
DA13 to 0 = H'0040 to H'3FFF
10 0 0 0 0 0.493 s
1 1 1 1 Setting
prohibited
         
Note: * Indicates the conversion cycle when specific DA3 to DA0 bits are fixed.