Datasheet

Rev. 2.00 Aug. 20, 2008 Page xl of xlviii
Figure 31.28 SSU Timing (Master, CPHS = 1)....................................................................... 1150
Figure 31.29 SSU Timing (Master, CPHS = 0)....................................................................... 1151
Figure 31.30 SSU Timing (Slave, CPHS = 1) ......................................................................... 1151
Figure 31.31 SSU Timing (Slave, CPHS = 0) ......................................................................... 1152
Figure 31.32 I
2
C Bus Interface Input/Output Timing .............................................................. 1154
Figure 31.33 LPC Interface (LPC) Timing..............................................................................1155
Figure 31.34 Timing of RM_REF-CLK and RMII Signals..................................................... 1156
Figure 31.35 RMII Transmit Timing.......................................................................................1157
Figure 31.36 RMII Receive Timing (Normal Operation)........................................................ 1157
Figure 31.37 RMII Receive Timing (When an Error is Detected) ..........................................1157
Figure 31.38 MDIO Input Timing ........................................................................................... 1158
Figure 31.39 MDIO Output Timing ........................................................................................1158
Figure 31.40 WOL Output Timing.......................................................................................... 1158
Figure 31.41 Data Signal Timing ............................................................................................ 1160
Figure 31.42 Load Condition...................................................................................................1160
Figure 31.43 JTAG ETCK Timing.......................................................................................... 1161
Figure 31.44 Reset Hold Timing ............................................................................................. 1162
Figure 31.45 JTAG Input/Output Timing................................................................................ 1162
Figure 31.46 Connecting Capacitors to VCC and VCL Pins................................................... 1165
Appendix
Figure C.1 Package Dimensions (PLBGA0176GA-A) ...........................................................1171
Figure C.2 Package Dimensions (PLQP0144KA-A)............................................................... 1172
Figure C.3 Package Dimensions (PTQP0144LC-A) ...............................................................1173