Datasheet

Rev. 2.00 Aug. 20, 2008 Page xli of xlviii
Tables
Section 1 Overview
Table 1.1
Pin Assignments in Each Operating Mode..................................................................... 7
Table 1.2 Pin Functions................................................................................................................ 14
Section 2 CPU
Table 2.1
Instruction Classification .............................................................................................41
Table 2.2 Operation Notation....................................................................................................... 42
Table 2.3 Data Transfer Instructions............................................................................................ 43
Table 2.4 Arithmetic Operations Instructions (1).........................................................................44
Table 2.4 Arithmetic Operations Instructions (2).........................................................................45
Table 2.5 Logic Operations Instructions ...................................................................................... 46
Table 2.6 Shift Instructions .......................................................................................................... 46
Table 2.7 Bit Manipulation Instructions (1)................................................................................. 47
Table 2.7 Bit Manipulation Instructions (2)................................................................................. 48
Table 2.8 Branch Instructions ...................................................................................................... 49
Table 2.9 System Control Instructions......................................................................................... 50
Table 2.10 Block Data Transfer Instructions ............................................................................... 51
Table 2.11 Addressing Modes......................................................................................................53
Table 2.12 Absolute Address Access Ranges ..............................................................................55
Table 2.13 Effective Address Calculation (1) ..............................................................................57
Table 2.13 Effective Address Calculation (2) ..............................................................................58
Section 3 MCU Operating Modes
Table 3.1
MCU Operating Mode Selection..................................................................................63
Section 4 Exception Handling
Table 4.1
Exception Types and Priority....................................................................................... 71
Table 4.2 Exception Handling Vector Table................................................................................ 72
Table 4.3 Status of CCR after Trap Instruction Exception Handling........................................... 76
Section 5 Interrupt Controller
Table 5.1
Pin Configuration......................................................................................................... 80
Table 5.2 Correspondence between Interrupt Source and ICR .................................................... 82
Table 5.3 Interrupt Sources, Vector Addresses, and Interrupt Priorities...................................... 90
Table 5.4 Interrupt Control Modes...............................................................................................93
Table 5.5 Interrupts Selected in Each Interrupt Control Mode ....................................................94
Table 5.6 Operations and Control Signal Functions in Each Interrupt Control Mode ................. 95
Table 5.7 Interrupt Response Times ..........................................................................................101
Table 5.8 Number of States in Interrupt Handling Routine Execution Status............................ 101