Datasheet

Section 10 16-Bit Free-Running Timer (FRT)
Rev. 2.00 Aug. 20, 2008 Page 380 of 1198
REJ09B0403-0200
10.2.5 Timer Control/Status Register (TCSR)
TCSR is used for counter clear selection and control of interrupt request signals.
Bit Bit Name
Initial
Value
R/W Description
7 to 4  All 0 R Reserved
These bits are always read as 0 and cannot be modified.
3 OCFA 0 R/(W)* Output Compare Flag A
Indicates that the FRC value matches the OCRA value.
[Setting condition]
When FRC = OCRA
[Clearing condition]
Read OCFA when OCFA = 1, then write 0 to OCFA
2 OCFB 0 R/(W)* Output Compare Flag B
Indicates that the FRC value matches the OCRB value.
[Setting condition]
When FRC = OCRB
[Clearing condition]
Read OCFB when OCFB = 1, then write 0 to OCFB
1 OVF 0 R/(W)* Overflow Flag
Indicates that the FRC has overflowed.
[Setting condition]
When FRC overflows (changes from H'FFFF to H'0000)
[Clearing condition]
Read OVF when OVF = 1, then write 0 to OVF
0 CCLRA 0 R/W Counter Clear A
Selects whether the FRC is to be cleared on compare-
match A (when the FRC and OCRA values match).
0: FRC clearing is disabled
1: FRC is cleared on compare-match A
Note: * Only 0 can be written to clear the flag.