Datasheet

Section 10 16-Bit Free-Running Timer (FRT)
Rev. 2.00 Aug. 20, 2008 Page 383 of 1198
REJ09B0403-0200
10.3 Operation Timing
10.3.1 FRC Increment Timing
Figure 10.2 shows the FRC increment timing with an internal clock source.
φ
Internal clock
FRC input
clock
FRC N – 1 N + 1N
Figure 10.2 Increment Timing with Internal Clock Source
10.3.2 Output Compare Output Timing
A compare-match signal occurs at the last state when the FRC and OCR values match (at the
timing when the FRC updates the counter value). Figure 10.3 shows the timing of this operation
for compare-match A.
φ
FRC
OCRA
NNN+1 N+1
NN
Compare-match
A signal
Figure 10.3 Timing of Output Compare A Output