Datasheet

Section 10 16-Bit Free-Running Timer (FRT)
Rev. 2.00 Aug. 20, 2008 Page 389 of 1198
REJ09B0403-0200
10.5.3 Conflict between OCR Write and Compare-Match
If a compare-match occurs during the state after an OCRA or OCRB write cycle, the write takes
priority and the compare-match signal is disabled. Figure 10.10 shows the timing for this type of
conflict.
If automatic addition of OCRAR and OCRAF to OCRA is selected, and a compare-match occurs
in the cycle following the OCRA, OCRAR, and OCRAF write cycle, the OCRA, OCRAR and
OCRAF write takes priority and the compare-match signal is disabled. Consequently, the result of
the automatic addition is not written to OCRA. Figure 10.11 shows the timing of this type of
conflict.
φ
Address OCR address
Internal write
signal
Compare-match
signal
FRC
Write data
Disabled
OCR N
M
N
N + 1
T
1
T
2
Write cycle of OCR
Figure 10.10 Conflict between OCR Write and Compare-Match
(When Automatic Addition Function is Not Used)