Datasheet

Rev. 2.00 Aug. 20, 2008 Page xlii of xlviii
Table 5.9 Interrupt Source Selection and Clearing Control ....................................................... 103
Section 6 Bus Controller (BSC)
Table 6.1
Pin Configuration....................................................................................................... 110
Table 6.2 Address Ranges and External Address Spaces........................................................... 119
Table 6.3 Bit Settings and Bus Specifications of Basic Bus Interface....................................... 120
Table 6.4 Bus Specifications for Basic Extended Area/Basic Bus Interface .............................120
Table 6.5 Bus Specifications for 256-Kbyte Extended Area/Basic Bus Interface ..................... 121
Table 6.6 Address-Data Multiplex Address Spaces................................................................... 123
Table 6.7 Bit Settings and Bus Specifications of Basic Bus Interface....................................... 124
Table 6.8 Bus Specifications for IOS Extended Area/Multiplex Bus Interface
(Address Cycle) ......................................................................................................... 124
Table 6.9 Bus Specifications for IOS Extended Area/Multiplex Bus Interface (Data Cycle).... 124
Table 6.10 Bus Specifications for 256-Kbyte Extended Area/Multiplex Bus Interface
(Address Cycle) ....................................................................................................... 125
Table 6.11 Bus Specifications for 256-Kbyte Extended Area/Multiplex Bus Interface
(Data Cycle)............................................................................................................. 125
Table 6.12 Address Range for IOS Signal Output ..................................................................... 126
Table 6.13 Data Buses Used and Valid Strobes......................................................................... 129
Table 6.14 Data Buses Used and Valid Strobes (Gluless Extension) ........................................ 130
Table 6.15 Pin States in Idle Cycle ............................................................................................ 157
Section 7 Data Transfer Controller (DTC)
Table 7.1
Correspondence between Interrupt Sources and DTCER .......................................... 167
Table 7.2 DTC Event Counter Conditions ................................................................................. 171
Table 7.3 Flag Status/Address Code .......................................................................................... 172
Table 7.4 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs.................... 176
Table 7.5 Register Functions in Normal Mode .......................................................................... 178
Table 7.6 Register Functions in Repeat Mode ........................................................................... 179
Table 7.7 Register Functions in Block Transfer Mode .............................................................. 180
Table 7.8 DTC Execution Status................................................................................................ 184
Table 7.9 Number of States Required for Each Execution Status.............................................. 184
Section 8 I/O Ports
Table 8.1
Port Functions ............................................................................................................ 190
Table 8.2 Port 1 Input Pull-Up MOS States............................................................................... 196
Table 8.3 Port 2 Input Pull-Up MOS States............................................................................... 201
Table 8.4 Port 3 Input Pull-Up MOS States............................................................................... 207
Table 8.5 Port 4 Input Pull-Up MOS States............................................................................... 215
Table 8.6 Port 6 Input Pull-Up MOS States............................................................................... 226
Table 8.7 Input Pull-Up MOS States .........................................................................................247
Table 8.8 Port D Input Pull-Up MOS States.............................................................................. 263