Datasheet

Section 11 8-Bit Timer (TMR)
Rev. 2.00 Aug. 20, 2008 Page 398 of 1198
REJ09B0403-0200
11.2.4 Timer Control Register (TCR)
TCR selects the TCNT clock source and the condition by which TCNT is cleared, and
enables/disables interrupt requests.
TCR_Y can be accessed when the TMRX/Y bit in TCONRS is 1. TCR_X can be accessed when
the TMRX/Y bit in TCONRS is 0. See section 11.2.6, Timer Connection Register S (TCONRS).
Bit Bit Name
Initial
Value
R/W Description
7 CMIEB 0 R/W Compare-Match Interrupt Enable B
Selects whether the CMFB interrupt request (CMIB) is
enabled or disabled when the CMFB flag in TCSR is set to
1.
0: CMFB interrupt request (CMIB) is disabled
1: CMFB interrupt request (CMIB) is enabled
6 CMIEA 0 R/W Compare-Match Interrupt Enable A
Selects whether the CMFA interrupt request (CMIA) is
enabled or disabled when the CMFA flag in TCSR is set to
1.
0: CMFA interrupt request (CMIA) is disabled
1: CMFA interrupt request (CMIA) is enabled
5 OVIE 0 R/W Timer Overflow Interrupt Enable
Selects whether the OVF interrupt request (OVI) is
enabled or disabled when the OVF flag in TCSR is set to
1.
0: OVF interrupt request (OVI) is disabled
1: OVF interrupt request (OVI) is enabled
4
3
CCLR1
CCLR0
0
0
R/W
R/W
Counter Clear 1 and 0
Specify the clearing conditions of TCNT.
00: Counter clear is disabled
01: Counter clear is enabled on compare-match A
10: Counter clear is enabled on compare-match B
11: Setting prohibited
2 to 0 CKS2 to
CKS0
All 0 R/W Clock Select 2 to 0
Select the clock input to TCNT and count condition,
together with the ICKS1 and ICKS0 bits in STCR. For
details, see table 11.1.