Datasheet

Section 11 8-Bit Timer (TMR)
Rev. 2.00 Aug. 20, 2008 Page 399 of 1198
REJ09B0403-0200
Table 11.1 (1) Clock Input to TCNT and Count Condition (TMR_0)
TCR STCR
CKS2 CKS1 CKS0 ICKS0 Description
0 0 0
X
Disables clock input
0 0 1
0
Increments at falling edge of internal clock φ/8
0 0 1
1
Increments at falling edge of internal clock φ/2
0 1 0
0
Increments at falling edge of internal clock φ/64
0 1 0
1
Increments at falling edge of internal clock φ/32
0 1 1
0
Increments at falling edge of internal clock φ/1024
0 1 1
1
Increments at falling edge of internal clock φ/256
1 0 0
X
Increments at overflow signal from TCNT_1*
1 0 1
X
Setting prohibited
1 1 X
X
Setting prohibited
Note: * If the TMR_0 clock input is set as the TCNT_1 overflow signal and the TMR_1 clock
input is set as the TCNT_0 compare-match signal simultaneously, a count-up clock
cannot be generated. Simultaneous setting of these conditions should be avoided.
[Legend] X: Don't care