Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 144 (20x20) 16-Bit 34 MHz I/O number 106

Rev. 2.00 Aug. 20, 2008 Page xliv of xlviii

Table 13.11 SSR Status Flags and Receive Data Handling ....................................................... 459

Table 13.12 SCI Interrupt Sources............................................................................................. 489

Table 13.13 SCI Interrupt Sources............................................................................................. 490

Section 15 Serial Communication Interface with FIFO (SCIF)

Table 15.1

Pin Configuration..................................................................................................... 509

Table 15.2 Register Access ........................................................................................................ 510

Table 15.3 Interrupt Control Function ....................................................................................... 515

Table 15.4 SCIF Output Setting................................................................................................. 527

Table 15.5 Example of Baud Rate Settings................................................................................ 528

Table 15.6 Correspondence Between LPC Interface I/O Address and the SCIF Registers ....... 539

Table 15.7 Register States.......................................................................................................... 540

Table 15.8 Interrupt Sources...................................................................................................... 541

Table 15.9 Interrupt Source, Vector Address, and Interrupt Priority......................................... 541

Section 16 Serial Pin Multiplexed Modes

Table 16.1

Pin Configuration..................................................................................................... 544

Section 17 Synchronous Serial Communication Unit (SSU)

Table 17.1

Pin Configuration..................................................................................................... 555

Table 17.2 Communication Modes and Pin States of SSI and SSO Pins................................... 568

Table 17.3 Communication Modes and Pin States of SSCK Pin ............................................... 569

Table 17.4 Communication Modes and Pin States of SCS Pin.................................................. 569

Table 17.5 Interrupt Sources...................................................................................................... 585

Section 18 I

C Bus Interface (IIC)

Table 18.1

Pin Configuration..................................................................................................... 590

Table 18.2 Transfer Format........................................................................................................ 594

Table 18.3 I

C bus Transfer Rate (1) ......................................................................................... 598

Table 18.3 I

C bus Transfer Rate (2) ......................................................................................... 599

Table 18.4 Flags and Transfer States (Master Mode) ................................................................ 606

Table 18.5 Flags and Transfer States (Slave Mode)...................................................................607

Table 18.6 Output Data Hold Time............................................................................................ 618

Table 18.7 ISCMBCR Setting.................................................................................................... 618

Table 18.8 I

C Bus Data Format Symbols ................................................................................. 620

Table 18.9 Examples of Operation Using the DTC ................................................................... 649

Table 18.10 IIC Interrupt Source ............................................................................................... 652

Table 18.11 I

C Bus Timing (SCL and SDA Outputs) .............................................................. 653

Table 18.12 Permissible SCL Rise Time (t

) Values................................................................. 654

Table 18.13 I

C Bus Timing (with Maximum Influence of t

)............................................. 656

Section 19 LPC Interface (LPC)

Table 19.1

Pin Configuration..................................................................................................... 670