Datasheet

Section 11 8-Bit Timer (TMR)
Rev. 2.00 Aug. 20, 2008 Page 414 of 1198
REJ09B0403-0200
No.
Timing of Switchover
by Means of CKS1
and CKS0 Bits TCNT Clock Operation
3 Clock switching from high
to low level∗
3
Clock before
switchover
Clock after
switchover
TCNT
clock
TCNT
CKS bit rewrite
N
N + 1 N + 2
*
4
4 Clock switching from high
to high level
Clock before
switchover
Clock after
switchover
TCNT
clock
TCNT
CKS bit rewrite
N
N + 1 N + 2
Notes: 1. Includes switching from low to stop, and from stop to low.
2. Includes switching from stop to high.
3. Includes switching from high to stop.
4. Generated on the assumption that the switchover is a falling edge; TCNT is
incremented.
11.6.5 Mode Setting with Cascaded Connection
If the 16-bit count mode and compare-match count mode are set simultaneously, the input clock
pulses for TCNT_0 and TCNT_1 are not generated, and thus the counters will stop operating.
Simultaneous setting of these two modes should be avoided.