Datasheet

Section 12 Watchdog Timer (WDT)
Rev. 2.00 Aug. 20, 2008 Page 423 of 1198
REJ09B0403-0200
TCNT value
H'00
Time
H'FF
WT/IT = 1
TME = 1
Write H'00 to
TCNT
WT/IT = 1
TME = 1
Write H'00 to
TCNT
518 system clocks
Internal reset signal
WT/IT:
TME:
OVF:
Overflow
OVF = 1*
Timer mode select bit
Timer enable bit
Overflow flag
Note: * After the OVF bit becomes 1, it is cleared to 0 by an internal reset.
The XRST bit is also cleared to 0.
Figure 12.2 Watchdog Timer Mode (RST/NMI = 1) Operation