Datasheet

Section 1 Overview
Rev. 2.00 Aug. 20, 2008 Page 1 of 1198
REJ09B0403-0200
Section 1 Overview
1.1 Overview
• High-speed H8S/2600 central processing unit with an internal 16-bit architecture
Upward-compatible with H8/300 and H8/300H CPUs on an object level
Sixteen 16-bit general registers
69 basic instructions
Multiplication and accumulation instructions
• Various peripheral functions
Data transfer controller (DTC)
14-bit PWM timer (PWMX)
16-bit free-running timer (FRT)
8-bit timer (TMR)
Watchdog timer (WDT)
Asynchronous or synchronous serial communication interface (SCI)
CRC operation circuit (CRC)
Serial communication interface with FIFO (SCIF)
Synchronous serial communication unit (SSU)
I
2
C bus interface (IIC)
LPC interface (LPC)
Ethernet controller (EtherC)
Direct memory access controller for Ethernet controller (E-DMAC)
USB function module (USB)*
1
10-bit A/D converter
Platform Environment Control Interface (PECI)*
2
Boundary scan (JTAG)
Clock pulse generator
Notes: 1. Supported only by the H8S/2472 Group.
2. Supported only by the H8S/2472 Group and the H8S/2462 Group.