Datasheet

Section 1 Overview
Rev. 2.00 Aug. 20, 2008 Page 3 of 1198
REJ09B0403-0200
1.2 Block Diagram
EVC
EtherC
E-DMAC
H8S/2600
CPU
DTC
RAM
40K
LPC
SCI_1, SCI_3
S
C
IF
SSU
FRT
IIC_0 to IIC_5
PECI*
J
T
AG
USB*
ROM
(Flash)
512K
(+16K UB)
Clock pulse
generator
14-bit PWM ×
4
8-bit timer × 4
WDT × 2
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port
E
Port F
P
ort D
P
ort C
Port
B
Po
rt
A
Port 9
Port 8
A/D converter
Interrupt controller
C
RC c
alculator
[Legend]
CPU: Central processing unit
DTC: Data transfer controller
EVC: Event counter
SCI: Serial communication interface
SCIF: Serial communication interface with FIFO
IIC: I
2
C bus interface
EtherC: Ethernet controller
E-DMAC: Direct memory access controller for Ethernet controller
SSU: Synchronous serial communication unit
USB: USB function module
FRT: 16-bit free running timer
PWM: 14-bit PWM timer
LPC: LPC interface
WDT: Watchdog timer
JTAG: Boundary scan
PECI: PECI interface
Bus controller
Notes: 1. Supported only by the H8S/2472 Group.
2. Supported only by the H8S/2472 Group and the H8S/2462 Group.
1
2
Figure 1.1 Internal Block Diagram