Datasheet

Section 15 Serial Communication Interface with FIFO (SCIF)
Rev. 2.00 Aug. 20, 2008 Page 508 of 1198
REJ09B0403-0200
Figure 15.1 shows a block diagram of the SCIF.
LPC
interface
Internal data bus
Bus interface
Modem
controller
P25/RI
P24/DCD
P26/DSR
P27/DTR
P64/CTS
P65/RTS
P50/TxDF
P51/RxDF
FRSR
FTSR
FTHR
FRBR
Transmit FIFO
(16 bytes)
Transmission
(1 byte)
Clock
selection/
divider
circuit
SCLK
FDLH
FDLL
Baud rate
generator
Transfer clock
SCIFCR
FIER
FIIR
FFCR
FLCR
FMCR
FLSR
FMSR
FSCR
Register
transmission/
reception
control
SCIF
interrupt
request
System clock
LCLK
Receive FIFO
(16 bytes)
Reception
(1 byte)
[Legend]
FRSR: Receive shift register
FTSR: Transmitter shift register
FRBR: Receive buffer register
FTHR: Transmitter holding register
FDLH, FDLL: Divisor latch H, L
FIER: Interrupt enable register
FIIR: Interrupt identification register
FFCR: FIFO control register
FLCR: Line control register
FMCR: Modem control register
FLSR: Line status register
FMSR: Modem status register
FSCR: Scratch pad register
SCIFCR: SCIF control register
Figure 15.1 Block Diagram of SCIF