Datasheet

Section 15 Serial Communication Interface with FIFO (SCIF)
Rev. 2.00 Aug. 20, 2008 Page 514 of 1198
REJ09B0403-0200
15.3.7 Interrupt Identification Register (FIIR)
FIIR consists of bits that identify interrupt sources. For details, see table 15.3.
Bit Bit Name Initial Value R/W Description
7
6
FIFOE1
FIFOE0
0
0
R
R
FIFO Enable 0, 1
These bits indicate the transmit/receive FIFO
setting.
00: Transmit/receive FIFOs disabled
11: Transmit/receive FIFOs enabled
5, 4  All 0 R Reserved
These bits are always read as 0. The initial value
should not be changed.
3
2
1
INTID2
INTID1
INTID0
0
0
0
R
R
R
Interrupt ID2, ID1, ID0
These bits Indicate the interrupt of the highest
priority among the pending interrupts.
000: Modem status
001: FTHR empty
010: Receive data ready
011: Receive line status
110: Character timeout (when the FIFO is enabled)
0 INTPEND 1 R Interrupt Pending
Indicates whether one or more interrupts are
pending.
0: Interrupt pending
1: No interrupt pending