Datasheet

Section 15 Serial Communication Interface with FIFO (SCIF)
Rev. 2.00 Aug. 20, 2008 Page 524 of 1198
REJ09B0403-0200
15.3.12 Modem Status Register (FMSR)
FMSR is a read-only register that indicates the status of or a change in the modem control pins.
Bit Bit Name Initial Value R/W Description
7 DCD 0 R Data Carrier Detect
Indicates the inverted state of the DCD input pin.
6 RI 0 R Ring Indicator
Indicates the inverted state of the RI input pin.
5 DSR 0 R Data Set Ready
Indicates the inverted state of the DSR input pin.
4 CTS 0 R Clear to Send
Indicates the inverted state of the CTS input pin.
3 DDCD 0 R Delta Data Carrier Indicator
Indicates a change in the DCD input signal after the
DDCD bit is read.
0: No change in the DCD input signal after FMSR
read
[Clearing condition]
FMSR read
1: A change in the DCD input signal after FMSR read
[Setting condition]
A change in the DCD input signal
2 TERI 0 R Trailing Edge Ring Indicator
Indicates a rise in the RI input signal after the TERI
bit is read.
0: No change in the RI input signal after FMSR read
[Clearing condition]
FMSR read
1: A rise in the RI input signal after FMSR read
[Setting condition]
A rise in the RI input pin