Datasheet

Section 15 Serial Communication Interface with FIFO (SCIF)
Rev. 2.00 Aug. 20, 2008 Page 526 of 1198
REJ09B0403-0200
15.3.14 SCIF Control Register (SCIFCR)
SCIFCR controls SCIF operations, and is accessible only from the CPU.
Bit Bit Name Initial Value R/W Description
7
6
SCIFOE1
SCIFOE0
0
0
R/W
R/W
These bits enable or disable PORT output of the
SCIF. The PORT function differs according to the
combination with the SCIF bit in HICR5 of the LPC.
For details, see table 15.4.
5  0 R/W Reserved
Do not change the initial value.
4 OUT2LOOP 0 R/W Enables or disables interrupts during a loopback
test.
0: Interrupt enabled
1: Interrupt disabled
3
2
CKSEL1
CKSEL0
0
0
R/W
R/W
These bits select the clock (SCLK) to be input to the
baud rate generator.
00: LCLK divided by 18
01: System clock divided by 11
10: Reserved for LCLK (not selectable)
11: Reserved for system clock (not selectable)
1 SCIFRST 0 R/W Resets the baud rate generator, FRSR, and FTSR.
0: Normal operation
1: Reset
0 REGRST 0 R/W Resets registers (except SCIFCR) accessible from
the H8S CPU or LPC interface.
0: Normal operation
1: Reset