Datasheet

Section 15 Serial Communication Interface with FIFO (SCIF)
Rev. 2.00 Aug. 20, 2008 Page 532 of 1198
REJ09B0403-0200
(3) Serial Data Reception
Figure 15.5 shows an example of the data reception flowchart.
Start reception
Read DR flag in FLSR
Read RXFIFOERR, BI, PE and OE
flag in FLSR
Read FRBR
Error processing
Read DR flag in FLSR
DR = 1
RXFIFOERR = 1,
BI = 1, FE = 1,
PE = 1, or OE = 1
Yes
No
No
No
No
Yes
Yes
All data read
(End of reception or reception standby)
Yes
Initialization
[1]
[2]
[3]
[4]
DR = 0
[1] Confirm that the DR flag in FLSR is 1 to ensure that
receive data is in the buffer. When the OUT2 bit in
FMCR and the ERBFI bit in FIER are set to 1, a
receive data ready interrupt occurs.
[2] Read the RXFIFOERR, BI, FE, PE, and OE flags in
FLSR to ensure that no error has occurred. If an
error has occurred, perform error processing. When
the OUT2 bit in FMCR and the ELSI bit in FIER are
set to 1, a receive line status interrupt occurs.
[3] Read the receive data in FRBR.
[4] Check the DR flag in FLSR. When the DR flag is
cleared to 0 and all data has been read, data reception
is complete.
Figure 15.5 Example of Data Reception Flowchart