Datasheet

Section 16 Serial Pin Multiplexed Modes
Rev. 2.00 Aug. 20, 2008 Page 545 of 1198
REJ09B0403-0200
16.3 Register Descriptions
Two registers are provided for serial pin multiplexed modes. Serial multiplexed mode register 0
(SMR0) enables or disables the serial pin multiplexing function, selects a serial pin multiplexed
mode out of 5 modes, and provides bits for port monitoring. Serial multiplexed mode register 1
(SMR1) provides bits for port monitoring and controls outputs on the relevant port pins.
• Serial multiplexed mode register 0 (SMR0)
• Serial multiplexed mode register 1 (SMR1)
16.3.1 Serial Multiplexed Mode Register 0 (SMR0)
Bit Bit Name
Initial
Value
R/W Description
7 DCD1  R Monitors the state of the DCD line in modes 1, 3, and
4.
6 RI1  R Monitors the state of the RI line in modes 1, 3, and 4.
5 DSR1  R Monitors the state of the DSR line in modes 1, 3, and
4.
4 SME 0 R/W Serial Pin Multiplex Enable
0: Pin multiplexing disabled
1: Pin multiplexing enabled
3  0 R Reserved
This bit is always read as 0. The write value should
always be 0.
2
1
0
SM2
SM1
SM0
0
0
0
R/W
R/W
R/W
Serial Pin Multiplexed Mode Select
These bits select a serial pin multiplexed mode. This
selection is only enabled when SME bit is 1.
000: Serial multiplexed mode 0
001: Serial multiplexed mode 1
010: Serial multiplexed mode 2
011: Serial multiplexed mode 3
100: Serial multiplexed mode 4
101: Reserved (Do not modify)
110: Reserved (Do not modify)
111: Reserved (Do not modify)