Datasheet

Section 16 Multiplex Mode
Rev. 2.00 Aug. 20, 2008 Page 550 of 1198
REJ09B0403-0200
16.4.4 Serial Pin Multiplexed Mode 3
(SMR0 Register [bits SM2, SM1, SM0] = [0 1 1])
This mode enables the use of COM2 by SCIF and COM1 by SCI_1. Since SCI_1 doesn't use any
hardware pins for flow control, emulation is possible using the internal registers.
Tx/Rx of COM1 are connected to RxD1/TxD1 of SCI_1, and other COM1 port signals are
controlled or monitored through bits in the internal registers. RxDF/TxDF of SCIF are connected
to Tx/Rx of COM2 and other SCIF signals are not used. DCD/RI/DSR/CTS of SCIF are fixed at 1.
RxD3 and TxD3 of SCI_3 are connected to Tx and Rx of COM3.
The states of DCD/RI/DSR of COM1 are reflected in bits DCD1/RI1/DSR1 of the SMR0 register,
and CTS of COM1 is reflected in bit CTS1 of the SMR1 register.
The values written to bits DTR1/RTS1 of the SMR1 register are output to DTR/RTS of COM1.
Figure 16.4 illustrates the pin connection in serial pin multiplexed mode 3.
COM2 COM3
SCI_1 SCI_3
BMC (H8S)
RxD1
TxD1
RxD3
TxD3
Rx Tx Rx Tx
COM1
DCD1
RI1
DSR1
SMR0
SCIF
P24 P25 P26 P27 P64 P65
P86 P87 P51 P50 P53 P52
DCD RI DSR DTR CTS RTS RxDF TxDF
DCD RI DSR DTR CTS RTS Rx Tx
CTS1
DTR1
RTS1
CTS3
SMR1
RTS3
1 1 1 Open 1 Open
Figure 16.4 Serial Pin Multiplexed Mode 3