Datasheet

Section 17 Synchronous Serial Communication Unit (SSU)
Rev. 2.00 Aug. 20, 2008 Page 555 of 1198
REJ09B0403-0200
17.2 Input/Output Pins
Table 17.1 shows the SSU pin configuration.
Table 17.1 Pin Configuration
Pin Name I/O Function
SSCK I/O SSU clock input/output
SSI I/O SSU data input/output
SSO I/O SSU data input/output
SCS I/O SSU chip select input/output
17.3 Register Descriptions
The SSU has the following registers.
• SS control register H (SSCRH)
• SS control register L (SSCRL)
• SS mode register (SSMR)
• SS enable register (SSER)
• SS status register (SSSR)
• SS control register 2 (SSCR2)
• SS transmit data register 0 (SSTDR0)
• SS transmit data register 1 (SSTDR1)
• SS transmit data register 2 (SSTDR2)
• SS transmit data register 3 (SSTDR3)
• SS receive data register 0 (SSRDR0)
• SS receive data register 1 (SSRDR1)
• SS receive data register 2 (SSRDR2)
• SS receive data register 3 (SSRDR3)
• SS shift register (SSTRSR)