Datasheet

Section 17 Synchronous Serial Communication Unit (SSU)
Rev. 2.00 Aug. 20, 2008 Page 560 of 1198
REJ09B0403-0200
17.3.4 SS Enable Register (SSER)
SSER performs transfer/receive control of synchronous serial communication and setting of
interrupt enable.
Bit Bit Name
Initial
Value
R/W Description
7 TE 0 R/W Transmit Enable
When this bit is set to 1, transmission is enabled.
6 RE 0 R/W Receive Enable
When this bit is set to 1, reception is enabled.
5, 4  All 0 R/W Reserved
These bits are always read as 0. The initial value
should not be changed.
3 TEIE 0 R/W Transmit End Interrupt Enable
When this bit is set to 1, a TEI interrupt request is
enabled.
2 TIE 0 R/W Transmit Interrupt Enable
When this bit is set to 1, a TXI interrupt request is
enabled.
1 RIE 0 R/W Receive Interrupt Enable
When this bit is set to 1, an RXI interrupt request and
an OEI interrupt request are enabled.
0 CEIE 0 R/W Conflict Error Interrupt Enable
When this bit is set to 1, a CEI interrupt request is
enabled.