Datasheet

Section 17 Synchronous Serial Communication Unit (SSU)
Rev. 2.00 Aug. 20, 2008 Page 561 of 1198
REJ09B0403-0200
17.3.5 SS Status Register (SSSR)
SSSR is a status flag register for interrupts.
Bit Bit Name
Initial
Value
R/W Description
7  0  Reserved
This bit is always read as 0. The initial value should not
be changed.
6 ORER 0 R/W Overrun Error
If the next data is received while RDRF = 1, an overrun
error occurs, indicating abnormal termination. SSRDR
stores 1-frame receive data before an overrun error
occurs and loses data to be received later. While ORER
= 1, consecutive serial reception cannot be continued.
Serial transmission cannot be continued, either.
[Setting condition]
When one byte of the next reception is completed with
RDRF = 1
[Clearing condition]
When writing 0 after reading ORER = 1
5, 4  All 0 R/W Reserved
These bits are always read as 0. The initial value
should not be changed.
3 TEND 1 R Transmit End
[Setting condition]
• When the last bit of transmit data is transmitted
while the TENDSTS bit in SSCR2 is cleared to 0
and the TDRE bit is set to 1
• After the last bit of transmit data is transmitted while
the TENDSTS bit in SSCR2 is set to 1 and the
TDRE bit is set to 1
[Clearing conditions]
• When writing 0 after reading TEND = 1
• When writing data to SSTDR