Datasheet

Section 17 Synchronous Serial Communication Unit (SSU)
Rev. 2.00 Aug. 20, 2008 Page 578 of 1198
REJ09B0403-0200
17.4.6 SCS Pin Control and Conflict Error
When bits CSS1 and CSS0 in SSCRH are specified to B'10 and the SSUMS bit in SSCRL is
cleared to 0, the SCS pin functions as an input (Hi-Z) to detect a conflict error. The arbitration
detection period is from setting the MSS bit in SSCRH to 1 to starting serial transfer and after
transfer ends. When a low level signal is input to the SCS pin within the period, a conflict error
occurs. At this time, the CE bit in SSSR is set to 1 and the MSS bit is cleared to 0.
Note: While the CE bit is set to 1, transmission or reception is not resumed. Clear the CE bit to 0
before resuming the transmission or reception.
CE
Data written
to SSTDR
Conflict error
detection period
Worst time for
internally clocking SCS
MSS
Internal signal for
transfer enable
SCS output
External input to SCS
Internal-clocked SCS
(Hi-Z)
Figure 17.10 Conflict Error Detection Timing (Before Transfer)
φ
SCS
MSS
CE
(Hi-Z)
Transfer
end
Conflict error detection period
Internal signal for
transfer enable
Figure 17.11 Conflict Error Detection Timing (After Transfer End)