Datasheet

Section 18 I
2
C Bus Interface (IIC)
Rev. 2.00 Aug. 20, 2008 Page 625 of 1198
REJ09B0403-0200
SDA
(master output)
SDA
(slave output)
21436587989
A
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 0
ICDRE
IRTR
ICDR
SCL
(master output)
Stop condition issuance
Data 2
[9] ICDR write
[9] IRIC clear
[12] IRIC clear
[11] ACKB read
[12] BBSY set to 1 and
SCP cleared to 0
(Stop condition issuance)
IRIC
A
[10]
[7]
Data 1
Data 1
Data 2
User processing
Figure 18.9 Stop Condition Issuance Operation Timing Example in Master Transmit Mode
(MLS = WAIT = 0)
18.4.4 Master Receive Operation
In I
2
C bus format master receive mode, the master device outputs the receive clock, receives data,
and returns an acknowledge signal. The slave device transmits data.
The master device transmits data containing the slave address and R/W (1: read) in the first frame
following the start condition issuance in master transmit mode, selects the slave device, and then
switches the mode for receive operation.