Datasheet

Section 18 I
2
C Bus Interface (IIC)
Rev. 2.00 Aug. 20, 2008 Page 628 of 1198
REJ09B0403-0200
SDA
(master output)
SDA
(slave output)
21
4
3
65
8
7
1
2
99
A
A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
IRTR
ICDRF
ICDRR
SCL
(master output)
Master transmit mode
Master receive mode
Data 1
Data 1 Data 2
[1]
TRS cleared to 0
[2] ICDR read
(Dummy read)
[1] IRIC clear
SCL is fixed low until ICDR is read SCL is fixed low until ICDR is read
[4] IRIC clear
User processing
IRIC
[3]
[6] ICDR read
(Data 1)
Undefined value
Figure 18.11 Master Receive Mode Operation Timing Example
(MLS = WAIT = 0, HNDS = 1)
SDA
(master output)
SDA
(slave output)
21
4
3
65
8
7
9978
A
A
Bit 7Bit 1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
IRIC
ICDRF
ICDRR
SCL
(master output)
Data 3
Data 2
Data 1 Data 2
Data 3
[9] IRIC clear
User processing
IRTR
[8] [3]
Bit 0
[11] BBSY cleared to 0 and
SCP cleared to 0
(Stop condition instruction issuance)
[4] IRIC clear [7] ICDR read
(Data 2)
[10] ICDR read
(Data 3)
[6] ACKB set to 1
Bit 0
Stop condition generation
SCL is fixed low until ICDR is read SCL is fixed low until ICDR is read
Figure 18.12 Stop Condition Issuance Timing Example in Master Receive Mode
(MLS = WAIT = 0, HNDS = 1)