Datasheet

Section 18 I
2
C Bus Interface (IIC)
Rev. 2.00 Aug. 20, 2008 Page 654 of 1198
REJ09B0403-0200
4. SCL and SDA input are sampled in synchronization with the internal clock. The AC timing
therefore depends on the system clock cycle t
cyc
, as shown in section 31, Electrical
Characteristics. Note that the I
2
C bus interface AC timing specification will not be met with a
system clock frequency of less than 5 MHz.
5. The I
2
C bus interface specification for the SCL rise time t
sr
is 1000 ns or less (300 ns for high-
speed mode). In master mode, the I
2
C bus interface monitors the SCL line and synchronizes
one bit at a time during communication. If t
sr
(the time for SCL to go from low to V
IH
) exceeds
the time determined by the input clock of the I
2
C bus interface, the high period of SCL is
extended. The SCL rise time is determined by the pull-up resistance and load capacitance of
the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance
and load capacitance so that the SCL rise time does not exceed the values given in table 18.12.
Table 18.12 Permissible SCL Rise Time (t
sr
) Values
Time Indication [ns]
TCSS IICXn
t
cyc
Indi-
cation
I
2
C Bus Specification
(Max.)
φ = 20 MHz φ = 25 MHz φ = 34 MHz
Standard
mode
1000 375 300 221 0 7.5 t
cyc
High-speed
mode
300 300 300 221
0
1 Standard
mode
1000 875 700 515
1 0
17.5 t
cyc
High-speed
mode
300 300 300 300
Standard
mode
1000 1000 1000 1000 1 1 37.5 t
cyc
High-speed
mode
300 300 300 300
Note: n = 0 to 5