Datasheet

Section 19 LPC Interface (LPC)
Rev. 2.00 Aug. 20, 2008 Page 667 of 1198
REJ09B0403-0200
Figure 19.1 shows a block diagram of the LPC.
IDR3
IDR2
IDR1
LADR1
LADR2
LADR3
TWR0MW
ODR2
ODR3
ODR1
STR3
STR2
STR1
TWR0SW
SERIRQ
CLKRUN
LSCI
LSMI
PME
LPCPD
LRESET
LCLK
LFRAME
OBEI
IBFI1
IBFI2
IBFI3
ERRI
GA20
SIRQCR0 to 5
HISEL
LSCIE
LSCIB
LSCI input
LSMIE
LSMIB
LSMI input
PMEE
PMEB
PME input
Module data bus
Cycle detection
Serial → parallel conversion
Serial ← parallel conversion
Address match
SYNC output
Parallel → serial conversion
Control logic
Internal interrupt
control
[Legend]
HICR0 to HICR5:
LADR12H, LADR12L:
LADR3H, LADR3L:
IDR1 to IDR3:
ODR1 to ODR3:
STR1 to STR3:
TWR1 to
TWR15
TWR1 to
TWR15
LAD0 to
LAD3
HICR0 to HICR5
Host interface control registers 0 to 5
LPC channel 1, 2 address registers 12H and 12L
LPC channel 3 address registers 3H and 3L
Input data registers 1 to 3
Output data registers 1 to 3
Status registers 1 to 3
TWR0MW:
TWR0SW:
TWR1 to TWR15:
SIRQCR0 to SIRQCR5:
HISEL:
Bidirectional data register 0MW
Bidirectional data register 0SW
Bidirectional data registers 1 to 15
SERIRQ control registers 0 to 5
Host interface select register
BTDTR
FIFO
(IN)
BTDTR
FIFO
(OUT)
LADR12
Figure 19.1 Block Diagram of LPC