Datasheet

Section 19 LPC Interface (LPC)
Rev. 2.00 Aug. 20, 2008 Page 669 of 1198
REJ09B0403-0200
19.3 Register Descriptions
The LPC has the following registers.
• Host interface control register 0 (HICR0)
• Host interface control register 1 (HICR1)
• Host interface control register 2 (HICR2)
• Host interface control register 3 (HICR3)
• Host interface control register 4 (HICR4)
• Host interface control register 5 (HICR5)
• Pin function control register (PINFNCR)
• LPC channel 1, 2 address register H, L (LADR12H, LADR12L)
• LPC channel 3 address register H, L (LADR3H, LADR3L)
• Input data register 1 (IDR1)
• Input data register 2 (IDR2)
• Input data register 3 (IDR3)
• Output data register 1 (ODR1)
• Output data register 2 (ODR2)
• Output data register 3 (ODR3)
• Status register 1 (STR1)
• Status register 2 (STR2)
• Status register 3 (STR3)
• Bidirectional data registers 0 to 15 (TWR0 to TWR15)
• SERIRQ control register 0 (SIRQCR0)
• SERIRQ control register 1 (SIRQCR1)
• SERIRQ control register 2 (SIRQCR2)
• SERIRQ control register 3 (SIRQCR3)
• SERIRQ control register 4 (SIRQCR4)
• SERIRQ control register 5 (SIRQCR5)
• Host interface select register (HISEL)
• SCIF address register H, L (SCIFADRH, SCIFADRL)