Datasheet

Section 19 LPC Interface (LPC)
Rev. 2.00 Aug. 20, 2008 Page 683 of 1198
REJ09B0403-0200
R/W
Bit Bit Name Initial Value Slave Host Description
1 SMICENBL 0 R/W  Enables or disables the use of the SMIC interface
included in channel 3. When the LPC3E bit in
HICR0 is 0, this bit is valid.
0: SMIC interface operation is disabled
No address (LADR3) matches for SMICFLG,
SSMICCSR, or SMICDTR
1: SMIC interface operation is enabled
0 BTENBL 0 R/W  Enables or disables the use of the BT interface
included in channel 3. When the LPC3E bit in
HICR0 is 0, this bit is valid.
0: BT interface operation is disabled
No address (LADR3) matches for BTIMSR,
BTCR, or BTDTR
1: BT interface operation is enabled
19.3.4 Host Interface Control Register 5 (HICR5)
HICR5 enables or disables the operation of the SCIF interface, and controls OBEI interrupts.
R/W
Bit Bit Name
Initial
Value Slave Host
Description
7 to 2  All 0 R/W  Reserved
The initial value bit should not be changed.
1 SCIFE 0 R/W  SCIF Enable
Enables or disables access from the LPC host of
the SCIF.
0: Disables access to the SCIF from the LPC host
1: Enables access to the SCIF from the LPC host
0  0 R/W  Reserved
The initial value should not be changed.