Datasheet

Section 19 LPC Interface (LPC)
Rev. 2.00 Aug. 20, 2008 Page 730 of 1198
REJ09B0403-0200
19.3.30 BT Data Buffer (BTDTR)
BTDTR is used to implement the BT mode. BTDTR consists of two FIFOs: the host write transfer
FIFO and the host read transfer FIFO. Their capacities are 64 bytes each. When using BTDTR,
enable FIFO by means of the bits FSEL0 and FSEL1.
R/W
Bit Bit Name
Initial
Value Slave Host Description
7 to 0 bit7 to bit0 Undefined R/W R/W The data written by the host is stored in FIFO (64
bytes) for host write transfer and read out by the
slave in order of host writing. The data written by the
slave is stored in FIFO (64 bytes) for host read
transfer and read out by the host in order of slave
writing.
19.3.31 BT Interrupt Mask Register (BTIMSR)
BTIMSR is one of the registers used to implement BT mode. The BTIMSR register contains the
bits used to control the interrupts to the host.
R/W
Bit Bit Name
Initial
Value Slave Host Description
7 BMC_
HWRST
0 R/(W)*
2
R/(W)*
1
Slave Reset
Performs a reset from the host to the slave. The
host can only write a 1. Writing a 0 to this bit is
invalid. The host will always return a 0 on read
out. Setting the RSTRENBL bit enables a 1 to be
read from the host.
0: The reset is cancelled
[Clearing condition]
When the slave writes a 0, after a 1 has been
read from BMC_HWRST.
1: The reset is in progress.
[Setting condition]
When the host writes a 1.
6
5


0
0
R/W
R/W
R/W
R/W
Reserved