Datasheet

Section 19 LPC Interface (LPC)
Rev. 2.00 Aug. 20, 2008 Page 735 of 1198
REJ09B0403-0200
ADDRStart
LFRAME
LAD3 to
LAD0
Number of clocks
LCLK
TAR Sync Data TAR Start
Cycle type,
direction,
and size
114 12221
Figure 19.2 Typical LFRAME Timing
ADDRStart
LFRAME
LAD3 to LAD0
LCLK
TAR Sync
Cycle type,
direction,
and size
Slave must stop driving
Too many Syncs
cause timeout
Master will
drive high
Figure 19.3 Abort Mechanism
19.4.3 SMIC Mode Transfer Flow
Figure 19.4 shows the write transfer flow and figure 19.5 shows the read transfer flow in SMIC
mode.