Datasheet

Section 19 LPC Interface (LPC)
Rev. 2.00 Aug. 20, 2008 Page 744 of 1198
REJ09B0403-0200
Table 19.8 shows the scope of the LPC interface pin shutdown.
Table 19.8 Scope of LPC Interface Pin Shutdown
Abbreviation Port
Scope of
Shutdown
I/O Notes
LAD3 to LAD0 PE3 to P30 O I/O Hi-Z
LFRAME PE4 O Input Hi-Z
LRESET PE5 X Input LPC hardware reset function is active
LCLK PE6 O Input Hi-Z
SERIRQ PE7 O I/O Hi-Z
LSCI PD0 ∆ I/O Hi-Z, only when LSCIE = 1
LSMI PD1 ∆ I/O Hi-Z, only when LSMIE = 1
PME PD2 ∆ I/O Hi-Z, only when PMEE = 1
GA20 PD3 ∆ I/O Hi-Z, only when FGA20E = 1
CLKRUN PD4 O Input Hi-Z
LPCPD PD5 X Input Needed to clear shutdown state
[Legend]
O: Pin that is shutdown by the shutdown function
∆: Pin that is shutdown only when the LPC function is selected by register setting
X: Pin that is not shutdown
In the LPC shutdown state, the LPC's internal state and some register bits are initialized. The order
of priority of LPC shutdown and reset states is as follows.
1. System reset (reset by RES pin input, or WDT0 overflow)
All register bits, including bits LPC4E to LPC1E, are initialized.
2. LPC hardware reset (reset by LRESET pin input)
LRSTB, SDWNE, and SDWNB bits are cleared to 0.
3. LPC software reset (reset by LRSTB)
SDWNE and SDWNB bits are cleared to 0.
4. LPC hardware shutdown
SDWNB bit is cleared to 0.
5. LPC software shutdown
The scope of the initialization in each mode is shown in table 19.9.