Datasheet

Section 20 Ethernet Controller (EtherC)
Rev. 2.00 Aug. 20, 2008 Page 764 of 1198
REJ09B0403-0200
20.3.2 EtherC Status Register (ECSR)
ECSR is a 32-bit readable/writable register and indicates the status in the EtherC. This status can
be notified to the CPU by interrupts. When 1 is written to the PSRTO, LCHNG, MPD, and ICD,
the corresponding flags can be cleared. Writing 0 does not affect the flag. For bits that generate
interrupt, the interrupt can be enabled or disabled according to the corresponding bit in ECSIPR.
The interrupts generated due to this status register are indicated in the ECI bit in EESR.
Bit Bit Name
Initial
Value
R/W Description
31 to 5  All 0 R Reserved
These bits are always read as 0. The initial value
should not be changed.
4 PSRTO 0 R/W PAUSE Frame Retransmission Retry Over
Indicates that during the retransmission of PAUSE
frames when the flow control is enabled, the number
of retries has exceeded the upper limit set in the
automatic PAUSE frame retransmission count set
register (TPAUSER).
0: Number of PAUSE frame retransmissions has not
exceeded the upper limit
1: Number of PAUSE frame retransmissions has
exceeded the upper limit
3  0 R Reserved
This bit is always read as 0. The initial value should
not be changed.
2 LCHNG 0 R/W Link Signal Change
Indicates that the LNKSTA signal input from the PHY
has changed from high to low or low to high.
To check the current Link state, refer to the LMON bit
in the PHY status register (PSR).
0: Changes in the LNKSTA signal are not detected
1: Changes in the LNKSTA signal are detected (high
to low or low to high)